x86/apic/
x2apic.rs

1//! x2APIC, the most recent APIC on x86 for large servers with more than 255 cores.
2use bit_field::BitField;
3
4use super::*;
5use crate::msr::{
6    rdmsr, wrmsr, IA32_APIC_BASE, IA32_TSC_DEADLINE, IA32_X2APIC_APICID, IA32_X2APIC_EOI,
7    IA32_X2APIC_ESR, IA32_X2APIC_ICR, IA32_X2APIC_LDR, IA32_X2APIC_LVT_LINT0,
8    IA32_X2APIC_LVT_TIMER, IA32_X2APIC_SELF_IPI, IA32_X2APIC_SIVR, IA32_X2APIC_VERSION,
9};
10
11/// Represents an x2APIC driver instance.
12#[derive(Debug)]
13pub struct X2APIC {
14    /// Initial base msr register value.
15    base: u64,
16}
17
18impl Default for X2APIC {
19    fn default() -> Self {
20        X2APIC { base: 0x0 }
21    }
22}
23
24impl X2APIC {
25    /// Create a new x2APIC driver object for the local core.
26    ///
27    /// # Notes
28    /// The object needs to be initialized by calling `attach()` first which
29    /// enables the x2APIC. There should be only one x2APIC object created per
30    /// core.
31    pub const fn new() -> Self {
32        X2APIC { base: 0x0 }
33    }
34
35    /// Attach to APIC (enable x2APIC mode, initialize LINT0)
36    pub fn attach(&mut self) {
37        // Enable
38        unsafe {
39            // Enable x2APIC mode globally
40            self.base = rdmsr(IA32_APIC_BASE);
41            self.base.set_bit(10, true); // Enable x2APIC
42            self.base.set_bit(11, true); // Enable xAPIC
43            wrmsr(IA32_APIC_BASE, self.base);
44
45            // Enable this XAPIC (set bit 8, spurious IRQ vector 15)
46            let svr: u64 = 1 << 8 | 15;
47            wrmsr(IA32_X2APIC_SIVR, svr);
48
49            // TODO: Fix magic number?
50            let lint0 = 1 << 16 | (1 << 15) | (0b111 << 8) | 0x20;
51            wrmsr(IA32_X2APIC_LVT_LINT0, lint0);
52
53            let _esr = rdmsr(IA32_X2APIC_ESR);
54        }
55    }
56
57    /// Detach from APIC (disable x2APIC and xAPIC mode).
58    pub fn detach(&mut self) {
59        unsafe {
60            self.base = rdmsr(IA32_APIC_BASE);
61            self.base.set_bit(10, false); // x2APIC
62            self.base.set_bit(11, false); // xAPIC
63            wrmsr(IA32_APIC_BASE, self.base);
64        }
65    }
66
67    /// Send an IPI to yourself.
68    ///
69    /// # Safety
70    /// Will interrupt core with `vector`.
71    pub unsafe fn send_self_ipi(&self, vector: u64) {
72        wrmsr(IA32_X2APIC_SELF_IPI, vector);
73    }
74}
75
76/// Abstracts common interface of APIC (x2APIC, xAPIC) hardware devices.
77impl ApicControl for X2APIC {
78    /// Is a bootstrap processor?
79    fn bsp(&self) -> bool {
80        (self.base & (1 << 8)) > 0
81    }
82
83    /// Read local x2APIC ID.
84    fn id(&self) -> u32 {
85        unsafe { rdmsr(IA32_X2APIC_APICID) as u32 }
86    }
87
88    /// In x2APIC mode, the 32-bit logical x2APIC ID, can be read from LDR.
89    fn logical_id(&self) -> u32 {
90        unsafe { rdmsr(IA32_X2APIC_LDR) as u32 }
91    }
92
93    /// Read APIC version.
94    fn version(&self) -> u32 {
95        unsafe { rdmsr(IA32_X2APIC_VERSION) as u32 }
96    }
97
98    /// Enable TSC timer
99    fn tsc_enable(&mut self, vector: u8) {
100        unsafe {
101            wrmsr(IA32_TSC_DEADLINE, 0);
102
103            let mut lvt: u64 = rdmsr(IA32_X2APIC_LVT_TIMER);
104            lvt &= !0xff;
105            lvt |= vector as u64;
106
107            // Unmask timer IRQ
108            lvt.set_bit(16, false);
109
110            // Enable TSC deadline mode
111            lvt.set_bit(17, false);
112            lvt.set_bit(18, true);
113            wrmsr(IA32_X2APIC_LVT_TIMER, lvt);
114        }
115    }
116
117    /// Set tsc deadline.
118    fn tsc_set(&self, value: u64) {
119        unsafe {
120            crate::fence::mfence();
121            wrmsr(IA32_TSC_DEADLINE, value);
122        }
123    }
124
125    /// End Of Interrupt -- Acknowledge interrupt delivery.
126    fn eoi(&mut self) {
127        unsafe {
128            wrmsr(IA32_X2APIC_EOI, 0);
129        }
130    }
131
132    /// Send a INIT IPI to a core.
133    unsafe fn ipi_init(&mut self, core: ApicId) {
134        let icr = Icr::for_x2apic(
135            0,
136            core,
137            DestinationShorthand::NoShorthand,
138            DeliveryMode::Init,
139            DestinationMode::Physical,
140            DeliveryStatus::Idle,
141            Level::Assert,
142            TriggerMode::Level,
143        );
144        self.send_ipi(icr);
145    }
146
147    /// Deassert INIT IPI.
148    unsafe fn ipi_init_deassert(&mut self) {
149        let icr = Icr::for_x2apic(
150            0,
151            ApicId::X2Apic(0),
152            // INIT deassert is always sent to everyone, so we are supposed to specify:
153            DestinationShorthand::AllIncludingSelf,
154            DeliveryMode::Init,
155            DestinationMode::Physical,
156            DeliveryStatus::Idle,
157            Level::Deassert,
158            TriggerMode::Level,
159        );
160        self.send_ipi(icr);
161    }
162
163    /// Send a STARTUP IPI to a core.
164    unsafe fn ipi_startup(&mut self, core: ApicId, start_page: u8) {
165        let icr = Icr::for_x2apic(
166            start_page,
167            core,
168            DestinationShorthand::NoShorthand,
169            DeliveryMode::StartUp,
170            DestinationMode::Physical,
171            DeliveryStatus::Idle,
172            Level::Assert,
173            TriggerMode::Edge,
174        );
175        self.send_ipi(icr);
176    }
177
178    /// Send a generic IPI.
179    unsafe fn send_ipi(&mut self, icr: Icr) {
180        wrmsr(IA32_X2APIC_ESR, 0);
181        wrmsr(IA32_X2APIC_ESR, 0);
182
183        wrmsr(IA32_X2APIC_ICR, icr.0);
184
185        loop {
186            let icr = rdmsr(IA32_X2APIC_ICR);
187            if (icr >> 12 & 0x1) == 0 {
188                break;
189            }
190            if rdmsr(IA32_X2APIC_ESR) > 0 {
191                break;
192            }
193        }
194    }
195}
x86/apic/x2apic.rs

x86/apic/
x2apic.rs
