x86/
fence.rs

1//! Intel fence instructions
2
3use core::arch::asm;
4
5/// mfence -- Memory Fence
6///
7/// Performs a serializing operation on all load-from-memory and store-to-memory
8/// instructions that were issued prior the MFENCE instruction.
9pub fn mfence() {
10    unsafe { asm!("mfence") };
11}
12
13/// sfence -- Store Fence
14///
15/// Orders processor execution relative to all memory stores prior to the SFENCE
16/// instruction. The processor ensures that every store prior to SFENCE is
17/// globally visible before any store after SFENCE becomes globally visible.
18pub fn sfence() {
19    unsafe { asm!("sfence") };
20}
21
22/// lfence -- Load Fence
23///
24/// Performs a serializing operation on all load-from-memory instructions that
25/// were issued prior the LFENCE instruction. Specifically, LFENCE does not
26/// execute until all prior instructions have completed locally, and no later
27/// instruction begins execution until LFENCE completes.
28pub fn lfence() {
29    unsafe { asm!("lfence") };
30}
x86/fence.rs

x86/
fence.rs
