x86/vmx/vmcs.rs
1//! Virtual-machine control structure fields.
2//!
3//! See Intel SDM, Volume 3D, Appendix B.
4
5/// VM-execution, VM-exit, and VM-entry control fields.
6pub mod control {
7 use bitflags::bitflags;
8
9 // B.1.1.: 16-bit control fields
10 /// Virtual-processor identifier (VPID).
11 pub const VPID: u32 = 0x0;
12 /// Posted-interrupt notification vector.
13 pub const POSTED_INTERRUPT_NOTIFICATION_VECTOR: u32 = 0x2;
14 /// EPTP index.
15 pub const EPTP_INDEX: u32 = 0x4;
16
17 // B.2.1.: 64-bit control fields
18 /// Address of I/O bitmap A (full).
19 pub const IO_BITMAP_A_ADDR_FULL: u32 = 0x2000;
20 /// Address of I/O bitmap A (high).
21 pub const IO_BITMAP_A_ADDR_HIGH: u32 = 0x2001;
22 /// Address of I/O bitmap B (full).
23 pub const IO_BITMAP_B_ADDR_FULL: u32 = 0x2002;
24 /// Address of I/O bitmap B (high).
25 pub const IO_BITMAP_B_ADDR_HIGH: u32 = 0x2003;
26 /// Address of MSR bitmaps (full).
27 pub const MSR_BITMAPS_ADDR_FULL: u32 = 0x2004;
28 /// Address of MSR bitmaps (high).
29 pub const MSR_BITMAPS_ADDR_HIGH: u32 = 0x2005;
30 /// VM-exit MSR-store address (full).
31 pub const VMEXIT_MSR_STORE_ADDR_FULL: u32 = 0x2006;
32 /// VM-exit MSR-store address (high).
33 pub const VMEXIT_MSR_STORE_ADDR_HIGH: u32 = 0x2007;
34 /// VM-exit MSR-load address (full).
35 pub const VMEXIT_MSR_LOAD_ADDR_FULL: u32 = 0x2008;
36 /// VM-exit MSR-load address (high).
37 pub const VMEXIT_MSR_LOAD_ADDR_HIGH: u32 = 0x2009;
38 /// VM-entry MSR-load address (full).
39 pub const VMENTRY_MSR_LOAD_ADDR_FULL: u32 = 0x200A;
40 /// VM-entry MSR-load address (high).
41 pub const VMENTRY_MSR_LOAD_ADDR_HIGH: u32 = 0x200B;
42 /// Executive-VMCS pointer (full).
43 pub const EXECUTIVE_VMCS_PTR_FULL: u32 = 0x200C;
44 /// Executive-VMCS pointer (high).
45 pub const EXECUTIVE_VMCS_PTR_HIGH: u32 = 0x200D;
46 /// PML address (full).
47 pub const PML_ADDR_FULL: u32 = 0x200E;
48 /// PML address (high).
49 pub const PML_ADDR_HIGH: u32 = 0x200F;
50 /// TSC offset (full).
51 pub const TSC_OFFSET_FULL: u32 = 0x2010;
52 /// TSC offset (high).
53 pub const TSC_OFFSET_HIGH: u32 = 0x2011;
54 /// Virtual-APIC address (full).
55 pub const VIRT_APIC_ADDR_FULL: u32 = 0x2012;
56 /// Virtual-APIC address (high).
57 pub const VIRT_APIC_ADDR_HIGH: u32 = 0x2013;
58 /// APIC-access address (full).
59 pub const APIC_ACCESS_ADDR_FULL: u32 = 0x2014;
60 /// APIC-access address (high).
61 pub const APIC_ACCESS_ADDR_HIGH: u32 = 0x2015;
62 /// Posted-interrupt descriptor address (full).
63 pub const POSTED_INTERRUPT_DESC_ADDR_FULL: u32 = 0x2016;
64 /// Posted-interrupt descriptor address (high).
65 pub const POSTED_INTERRUPT_DESC_ADDR_HIGH: u32 = 0x2017;
66 /// VM-function controls (full).
67 pub const VM_FUNCTION_CONTROLS_FULL: u32 = 0x2018;
68 /// VM-function controls (high).
69 pub const VM_FUNCTION_CONTROLS_HIGH: u32 = 0x2019;
70 /// EPT pointer (full).
71 pub const EPTP_FULL: u32 = 0x201A;
72 /// EPT pointer (high).
73 pub const EPTP_HIGH: u32 = 0x201B;
74 /// EOI-exit bitmap 0 (full).
75 pub const EOI_EXIT0_FULL: u32 = 0x201C;
76 /// EOI-exit bitmap 0 (high).
77 pub const EOI_EXIT0_HIGH: u32 = 0x201D;
78 /// EOI-exit bitmap 1 (full).
79 pub const EOI_EXIT1_FULL: u32 = 0x201E;
80 /// EOI-exit bitmap 1 (high).
81 pub const EOI_EXIT1_HIGH: u32 = 0x201F;
82 /// EOI-exit bitmap 2 (full).
83 pub const EOI_EXIT2_FULL: u32 = 0x2020;
84 /// EOI-exit bitmap 2 (high).
85 pub const EOI_EXIT2_HIGH: u32 = 0x2021;
86 /// EOI-exit bitmap 3 (full).
87 pub const EOI_EXIT3_FULL: u32 = 0x2022;
88 /// EOI-exit bitmap 3 (high).
89 pub const EOI_EXIT3_HIGH: u32 = 0x2023;
90 /// EPTP-list address (full).
91 pub const EPTP_LIST_ADDR_FULL: u32 = 0x2024;
92 /// EPTP-list address (high).
93 pub const EPTP_LIST_ADDR_HIGH: u32 = 0x2025;
94 /// VMREAD-bitmap address (full).
95 pub const VMREAD_BITMAP_ADDR_FULL: u32 = 0x2026;
96 /// VMREAD-bitmap address (high).
97 pub const VMREAD_BITMAP_ADDR_HIGH: u32 = 0x2027;
98 /// VMWRITE-bitmap address (full).
99 pub const VMWRITE_BITMAP_ADDR_FULL: u32 = 0x2028;
100 /// VMWRITE-bitmap address (high).
101 pub const VMWRITE_BITMAP_ADDR_HIGH: u32 = 0x2029;
102 /// Virtualization-exception information address (full).
103 pub const VIRT_EXCEPTION_INFO_ADDR_FULL: u32 = 0x202A;
104 /// Virtualization-exception information address (high).
105 pub const VIRT_EXCEPTION_INFO_ADDR_HIGH: u32 = 0x202B;
106 /// XSS-exiting bitmap (full).
107 pub const XSS_EXITING_BITMAP_FULL: u32 = 0x202C;
108 /// XSS-exiting bitmap (high).
109 pub const XSS_EXITING_BITMAP_HIGH: u32 = 0x202D;
110 /// ENCLS-exiting bitmap (full).
111 pub const ENCLS_EXITING_BITMAP_FULL: u32 = 0x202E;
112 /// ENCLS-exiting bitmap (high).
113 pub const ENCLS_EXITING_BITMAP_HIGH: u32 = 0x202F;
114 /// Sub-page-permission-table pointer (full).
115 pub const SUBPAGE_PERM_TABLE_PTR_FULL: u32 = 0x2030;
116 /// Sub-page-permission-table pointer (high).
117 pub const SUBPAGE_PERM_TABLE_PTR_HIGH: u32 = 0x2031;
118 /// TSC multiplier (full).
119 pub const TSC_MULTIPLIER_FULL: u32 = 0x2032;
120 /// TSC multiplier (high).
121 pub const TSC_MULTIPLIER_HIGH: u32 = 0x2033;
122
123 // B.3.1.: 32-bit control fields
124 /// Pin-based VM-execution controls.
125 pub const PINBASED_EXEC_CONTROLS: u32 = 0x4000;
126 /// Primary processor-based VM-execution controls.
127 pub const PRIMARY_PROCBASED_EXEC_CONTROLS: u32 = 0x4002;
128 /// Exception bitmap.
129 pub const EXCEPTION_BITMAP: u32 = 0x4004;
130 /// Page-fault error-code mask.
131 pub const PAGE_FAULT_ERR_CODE_MASK: u32 = 0x4006;
132 /// Page-fault error-code match.
133 pub const PAGE_FAULT_ERR_CODE_MATCH: u32 = 0x4008;
134 /// CR3-target count.
135 pub const CR3_TARGET_COUNT: u32 = 0x400A;
136 /// VM-exit controls.
137 pub const VMEXIT_CONTROLS: u32 = 0x400C;
138 /// VM-exit MSR-store count.
139 pub const VMEXIT_MSR_STORE_COUNT: u32 = 0x400E;
140 /// VM-exit MSR-load count.
141 pub const VMEXIT_MSR_LOAD_COUNT: u32 = 0x4010;
142 /// VM-entry controls.
143 pub const VMENTRY_CONTROLS: u32 = 0x4012;
144 /// VM-entry MSR-load count.
145 pub const VMENTRY_MSR_LOAD_COUNT: u32 = 0x4014;
146 /// VM-entry interruption-information field.
147 pub const VMENTRY_INTERRUPTION_INFO_FIELD: u32 = 0x4016;
148 /// VM-entry exception error code.
149 pub const VMENTRY_EXCEPTION_ERR_CODE: u32 = 0x4018;
150 /// VM-entry instruction length.
151 pub const VMENTRY_INSTRUCTION_LEN: u32 = 0x401A;
152 /// TPR threshold.
153 pub const TPR_THRESHOLD: u32 = 0x401C;
154 /// Secondary processor-based VM-execution controls.
155 pub const SECONDARY_PROCBASED_EXEC_CONTROLS: u32 = 0x401E;
156 /// PLE_Gap.
157 pub const PLE_GAP: u32 = 0x4020;
158 /// PLE_Window.
159 pub const PLE_WINDOW: u32 = 0x4022;
160
161 // B.4.1.: natural-width control fields
162 /// CR0 guest/host mask.
163 pub const CR0_GUEST_HOST_MASK: u32 = 0x6000;
164 /// CR4 guest/host mask.
165 pub const CR4_GUEST_HOST_MASK: u32 = 0x6002;
166 /// CR0 read shadow.
167 pub const CR0_READ_SHADOW: u32 = 0x6004;
168 /// CR4 read shadow.
169 pub const CR4_READ_SHADOW: u32 = 0x6006;
170 /// CR3-target value 0.
171 pub const CR3_TARGET_VALUE0: u32 = 0x6008;
172 /// CR3-target value 1.
173 pub const CR3_TARGET_VALUE1: u32 = 0x600A;
174 /// CR3-target value 2.
175 pub const CR3_TARGET_VALUE2: u32 = 0x600C;
176 /// CR3-target value 3.
177 pub const CR3_TARGET_VALUE3: u32 = 0x600E;
178
179 bitflags! {
180 /// Pin-based VM-execution controls.
181 ///
182 /// A set of bitmask flags useful when setting up [`PINBASED_EXEC_CONTROLS`] VMCS field.
183 ///
184 /// See Intel SDM, Volume 3C, Section 24.6.1.
185 pub struct PinbasedControls: u32 {
186 /// External-interrupt exiting.
187 const EXTERNAL_INTERRUPT_EXITING = 1 << 0;
188 /// NMI exiting.
189 const NMI_EXITING = 1 << 3;
190 /// Virtual NMIs.
191 const VIRTUAL_NMIS = 1 << 5;
192 /// Activate VMX-preemption timer.
193 const VMX_PREEMPTION_TIMER = 1 << 6;
194 /// Process posted interrupts.
195 const POSTED_INTERRUPTS = 1 << 7;
196 }
197 }
198
199 bitflags! {
200 /// Primary processor-based VM-execution controls.
201 ///
202 /// A set of bitmask flags useful when setting up [`PRIMARY_PROCBASED_EXEC_CONTROLS`] VMCS field.
203 ///
204 /// See Intel SDM, Volume 3C, Section 24.6.2, Table 24-6.
205 pub struct PrimaryControls: u32 {
206 /// Interrupt-window exiting.
207 const INTERRUPT_WINDOW_EXITING = 1 << 2;
208 /// Use TSC offsetting.
209 const USE_TSC_OFFSETTING = 1 << 3;
210 /// HLT exiting.
211 const HLT_EXITING = 1 << 7;
212 /// INVLPG exiting.
213 const INVLPG_EXITING = 1 << 9;
214 /// MWAIT exiting.
215 const MWAIT_EXITING = 1 << 10;
216 /// RDPMC exiting.
217 const RDPMC_EXITING = 1 << 11;
218 /// RDTSC exiting.
219 const RDTSC_EXITING = 1 << 12;
220 /// CR3-load exiting.
221 const CR3_LOAD_EXITING = 1 << 15;
222 /// CR3-store exiting.
223 const CR3_STORE_EXITING = 1 << 16;
224 /// CR8-load exiting.
225 const CR8_LOAD_EXITING = 1 << 19;
226 /// CR8-store exiting.
227 const CR8_STORE_EXITING = 1 << 20;
228 /// Use TPR shadow.
229 const USE_TPR_SHADOW = 1 << 21;
230 /// NMI-window exiting.
231 const NMI_WINDOW_EXITING = 1 << 22;
232 /// MOV-DR exiting
233 const MOV_DR_EXITING = 1 << 23;
234 /// Unconditional I/O exiting.
235 const UNCOND_IO_EXITING = 1 << 24;
236 /// Use I/O bitmaps.
237 const USE_IO_BITMAPS = 1 << 25;
238 /// Monitor trap flag.
239 const MONITOR_TRAP_FLAG = 1 << 27;
240 /// Use MSR bitmaps.
241 const USE_MSR_BITMAPS = 1 << 28;
242 /// MONITOR exiting.
243 const MONITOR_EXITING = 1 << 29;
244 /// PAUSE exiting.
245 const PAUSE_EXITING = 1 << 30;
246 /// Activate secondary controls.
247 const SECONDARY_CONTROLS = 1 << 31;
248 }
249 }
250
251 bitflags! {
252 /// Secondary processor-based VM-execution controls.
253 ///
254 /// A set of bitmask flags useful when setting up [`SECONDARY_PROCBASED_EXEC_CONTROLS`] VMCS field.
255 ///
256 /// See Intel SDM, Volume 3C, Section 24.6.2, Table 24-7.
257 pub struct SecondaryControls: u32 {
258 /// Virtualize APIC accesses.
259 const VIRTUALIZE_APIC = 1 << 0;
260 /// Enable EPT.
261 const ENABLE_EPT = 1 << 1;
262 /// Descriptor-table exiting.
263 const DTABLE_EXITING = 1 << 2;
264 /// Enable RDTSCP.
265 const ENABLE_RDTSCP = 1 << 3;
266 /// Virtualize x2APIC mode.
267 const VIRTUALIZE_X2APIC = 1 << 4;
268 /// Enable VPID.
269 const ENABLE_VPID = 1 << 5;
270 /// WBINVD exiting.
271 const WBINVD_EXITING = 1 << 6;
272 /// Unrestricted guest.
273 const UNRESTRICTED_GUEST = 1 << 7;
274 /// APIC-register virtualization.
275 const VIRTUALIZE_APIC_REGISTER = 1 << 8;
276 /// Virtual-interrupt delivery.
277 const VIRTUAL_INTERRUPT_DELIVERY = 1 << 9;
278 /// PAUSE-loop exiting.
279 const PAUSE_LOOP_EXITING = 1 << 10;
280 /// RDRAND exiting.
281 const RDRAND_EXITING = 1 << 11;
282 /// Enable INVPCID.
283 const ENABLE_INVPCID = 1 << 12;
284 /// Enable VM functions.
285 const ENABLE_VM_FUNCTIONS = 1 << 13;
286 /// VMCS shadowing.
287 const VMCS_SHADOWING = 1 << 14;
288 /// Enable ENCLS exiting.
289 const ENCLS_EXITING = 1 << 15;
290 /// RDSEED exiting.
291 const RDSEED_EXITING = 1 << 16;
292 /// Enable PML.
293 const ENABLE_PML = 1 << 17;
294 /// EPT-violation #VE.
295 const EPT_VIOLATION_VE = 1 << 18;
296 /// Conceal VMX from PT.
297 const CONCEAL_VMX_FROM_PT = 1 << 19;
298 /// Enable XSAVES/XRSTORS.
299 const ENABLE_XSAVES_XRSTORS = 1 << 20;
300 /// Mode-based execute control for EPT.
301 const MODE_BASED_EPT = 1 << 22;
302 /// Sub-page write permissions for EPT.
303 const SUB_PAGE_EPT = 1 << 23;
304 /// Intel PT uses guest physical addresses.
305 const INTEL_PT_GUEST_PHYSICAL = 1 << 24;
306 /// Use TSC scaling.
307 const USE_TSC_SCALING = 1 << 25;
308 /// Enable user wait and pause.
309 const ENABLE_USER_WAIT_PAUSE = 1 << 26;
310 /// Enable ENCLV exiting.
311 const ENCLV_EXITING = 1 << 28;
312 }
313 }
314
315 bitflags! {
316 /// VM-entry controls.
317 ///
318 /// A set of bitmask flags useful when setting up [`VMENTRY_CONTROLS`] VMCS field.
319 ///
320 /// See Intel SDM, Volume 3C, Section 24.8.
321 pub struct EntryControls: u32 {
322 /// Load debug controls.
323 const LOAD_DEBUG_CONTROLS = 1 << 2;
324 /// IA-32e mode guest.
325 const IA32E_MODE_GUEST = 1 << 9;
326 /// Entry to SMM.
327 const ENTRY_TO_SMM = 1 << 10;
328 /// Deactivate dual-monitor treatment.
329 const DEACTIVATE_DUAL_MONITOR = 1 << 11;
330 /// Load IA32_PERF_GLOBAL_CTRL.
331 const LOAD_IA32_PERF_GLOBAL_CTRL = 1 << 13;
332 /// Load IA32_PAT.
333 const LOAD_IA32_PAT = 1 << 14;
334 /// Load IA32_EFER.
335 const LOAD_IA32_EFER = 1 << 15;
336 /// Load IA32_BNDCFGS.
337 const LOAD_IA32_BNDCFGS = 1 << 16;
338 /// Conceal VMX from PT.
339 const CONCEAL_VMX_FROM_PT = 1 << 17;
340 /// Load IA32_RTIT_CTL.
341 const LOAD_IA32_RTIT_CTL = 1 << 18;
342 }
343 }
344
345 bitflags! {
346 /// VM-exit controls.
347 ///
348 /// A set of bitmask flags useful when setting up [`VMEXIT_CONTROLS`] VMCS field.
349 ///
350 /// See Intel SDM, Volume 3C, Section 24.7.
351 pub struct ExitControls: u32 {
352 /// Save debug controls.
353 const SAVE_DEBUG_CONTROLS = 1 << 2;
354 /// Host address-space size.
355 const HOST_ADDRESS_SPACE_SIZE = 1 << 9;
356 /// Load IA32_PERF_GLOBAL_CTRL.
357 const LOAD_IA32_PERF_GLOBAL_CTRL = 1 << 12;
358 /// Acknowledge interrupt on exit.
359 const ACK_INTERRUPT_ON_EXIT = 1 << 15;
360 /// Save IA32_PAT.
361 const SAVE_IA32_PAT = 1 << 18;
362 /// Load IA32_PAT.
363 const LOAD_IA32_PAT = 1 << 19;
364 /// Save IA32_EFER.
365 const SAVE_IA32_EFER = 1 << 20;
366 /// Load IA32_EFER.
367 const LOAD_IA32_EFER = 1 << 21;
368 /// Save VMX-preemption timer.
369 const SAVE_VMX_PREEMPTION_TIMER = 1 << 22;
370 /// Clear IA32_BNDCFGS.
371 const CLEAR_IA32_BNDCFGS = 1 << 23;
372 /// Conceal VMX from PT.
373 const CONCEAL_VMX_FROM_PT = 1 << 24;
374 /// Clear IA32_RTIT_CTL.
375 const CLEAR_IA32_RTIT_CTL = 1 << 25;
376 }
377 }
378}
379
380/// Fields used to access guest-state area.
381pub mod guest {
382 // B.1.2.: 16-bit guest-state fields
383 /// Guest ES selector.
384 pub const ES_SELECTOR: u32 = 0x800;
385 /// Guest CS selector.
386 pub const CS_SELECTOR: u32 = 0x802;
387 /// Guest SS selector.
388 pub const SS_SELECTOR: u32 = 0x804;
389 /// Guest DS selector.
390 pub const DS_SELECTOR: u32 = 0x806;
391 /// Guest FS selector.
392 pub const FS_SELECTOR: u32 = 0x808;
393 /// Guest GS selector.
394 pub const GS_SELECTOR: u32 = 0x80A;
395 /// Guest LDTR selector.
396 pub const LDTR_SELECTOR: u32 = 0x80C;
397 /// Guest TR selector.
398 pub const TR_SELECTOR: u32 = 0x80E;
399 /// Guest interrupt status.
400 pub const INTERRUPT_STATUS: u32 = 0x810;
401 /// PML index.
402 pub const PML_INDEX: u32 = 0x812;
403
404 // B.2.3.: 64-bit guest-state fields
405 /// VMCS link pointer (full).
406 pub const LINK_PTR_FULL: u32 = 0x2800;
407 /// VMCS link pointer (high).
408 pub const LINK_PTR_HIGH: u32 = 0x2801;
409 /// Guest IA32_DEBUGCTL (full).
410 pub const IA32_DEBUGCTL_FULL: u32 = 0x2802;
411 /// Guest IA32_DEBUGCTL (high).
412 pub const IA32_DEBUGCTL_HIGH: u32 = 0x2803;
413 /// Guest IA32_PAT (full).
414 pub const IA32_PAT_FULL: u32 = 0x2804;
415 /// Guest IA32_PAT (high).
416 pub const IA32_PAT_HIGH: u32 = 0x2805;
417 /// Guest IA32_EFER (full).
418 pub const IA32_EFER_FULL: u32 = 0x2806;
419 /// Guest IA32_EFER (high).
420 pub const IA32_EFER_HIGH: u32 = 0x2807;
421 /// Guest IA32_PERF_GLOBAL_CTRL (full).
422 pub const IA32_PERF_GLOBAL_CTRL_FULL: u32 = 0x2808;
423 /// Guest IA32_PERF_GLOBAL_CTRL (high).
424 pub const IA32_PERF_GLOBAL_CTRL_HIGH: u32 = 0x2809;
425 /// Guest PDPTE0 (full).
426 pub const PDPTE0_FULL: u32 = 0x280A;
427 /// Guest PDPTE0 (high).
428 pub const PDPTE0_HIGH: u32 = 0x280B;
429 /// Guest PDPTE1 (full).
430 pub const PDPTE1_FULL: u32 = 0x280C;
431 /// Guest PDPTE1 (high).
432 pub const PDPTE1_HIGH: u32 = 0x280D;
433 /// Guest PDPTE2 (full).
434 pub const PDPTE2_FULL: u32 = 0x280E;
435 /// Guest PDPTE2 (high).
436 pub const PDPTE2_HIGH: u32 = 0x280F;
437 /// Guest PDPTE3 (full).
438 pub const PDPTE3_FULL: u32 = 0x2810;
439 /// Guest PDPTE3 (high).
440 pub const PDPTE3_HIGH: u32 = 0x2811;
441 /// Guest IA32_BNDCFGS (full).
442 pub const IA32_BNDCFGS_FULL: u32 = 0x2812;
443 /// Guest IA32_BNDCFGS (high).
444 pub const IA32_BNDCFGS_HIGH: u32 = 0x2813;
445 /// Guest IA32_RTIT_CTL (full).
446 pub const IA32_RTIT_CTL_FULL: u32 = 0x2814;
447 /// Guest IA32_RTIT_CTL (high).
448 pub const IA32_RTIT_CTL_HIGH: u32 = 0x2815;
449
450 // B.3.3.: 32-bit guest-state fields
451 /// Guest ES limit.
452 pub const ES_LIMIT: u32 = 0x4800;
453 /// Guest CS limit.
454 pub const CS_LIMIT: u32 = 0x4802;
455 /// Guest SS limit.
456 pub const SS_LIMIT: u32 = 0x4804;
457 /// Guest DS limit.
458 pub const DS_LIMIT: u32 = 0x4806;
459 /// Guest FS limit.
460 pub const FS_LIMIT: u32 = 0x4808;
461 /// Guest GS limit.
462 pub const GS_LIMIT: u32 = 0x480A;
463 /// Guest LDTR limit.
464 pub const LDTR_LIMIT: u32 = 0x480C;
465 /// Guest TR limit.
466 pub const TR_LIMIT: u32 = 0x480E;
467 /// Guest GDTR limit.
468 pub const GDTR_LIMIT: u32 = 0x4810;
469 /// Guest IDTR limit.
470 pub const IDTR_LIMIT: u32 = 0x4812;
471 /// Guest ES access rights.
472 pub const ES_ACCESS_RIGHTS: u32 = 0x4814;
473 /// Guest CS access rights.
474 pub const CS_ACCESS_RIGHTS: u32 = 0x4816;
475 /// Guest SS access rights.
476 pub const SS_ACCESS_RIGHTS: u32 = 0x4818;
477 /// Guest DS access rights.
478 pub const DS_ACCESS_RIGHTS: u32 = 0x481A;
479 /// Guest FS access rights.
480 pub const FS_ACCESS_RIGHTS: u32 = 0x481C;
481 /// Guest GS access rights.
482 pub const GS_ACCESS_RIGHTS: u32 = 0x481E;
483 /// Guest LDTR access rights.
484 pub const LDTR_ACCESS_RIGHTS: u32 = 0x4820;
485 /// Guest TR access rights.
486 pub const TR_ACCESS_RIGHTS: u32 = 0x4822;
487 /// Guest interruptibility state.
488 pub const INTERRUPTIBILITY_STATE: u32 = 0x4824;
489 /// Guest activity state.
490 pub const ACTIVITY_STATE: u32 = 0x4826;
491 /// Guest SMBASE.
492 pub const SMBASE: u32 = 0x4828;
493 /// Guest IA32_SYSENTER_CS.
494 pub const IA32_SYSENTER_CS: u32 = 0x482A;
495 /// VMX-preemption timer value.
496 pub const VMX_PREEMPTION_TIMER_VALUE: u32 = 0x482E;
497
498 // B.4.3.: natural-width guest-state fields
499 /// Guest CR0.
500 pub const CR0: u32 = 0x6800;
501 /// Guest CR3.
502 pub const CR3: u32 = 0x6802;
503 /// Guest CR4.
504 pub const CR4: u32 = 0x6804;
505 /// Guest ES base.
506 pub const ES_BASE: u32 = 0x6806;
507 /// Guest CS base.
508 pub const CS_BASE: u32 = 0x6808;
509 /// Guest SS base.
510 pub const SS_BASE: u32 = 0x680A;
511 /// Guest DS base.
512 pub const DS_BASE: u32 = 0x680C;
513 /// Guest FS base.
514 pub const FS_BASE: u32 = 0x680E;
515 /// Guest GS base.
516 pub const GS_BASE: u32 = 0x6810;
517 /// Guest LDTR base.
518 pub const LDTR_BASE: u32 = 0x6812;
519 /// Guest TR base.
520 pub const TR_BASE: u32 = 0x6814;
521 /// Guest GDTR base.
522 pub const GDTR_BASE: u32 = 0x6816;
523 /// Guest IDTR base.
524 pub const IDTR_BASE: u32 = 0x6818;
525 /// Guest DR7.
526 pub const DR7: u32 = 0x681A;
527 /// Guest RSP.
528 pub const RSP: u32 = 0x681C;
529 /// Guest RIP.
530 pub const RIP: u32 = 0x681E;
531 /// Guest RFLAGS.
532 pub const RFLAGS: u32 = 0x6820;
533 /// Guest pending debug exceptions.
534 pub const PENDING_DBG_EXCEPTIONS: u32 = 0x6822;
535 /// Guest IA32_SYSENTER_ESP.
536 pub const IA32_SYSENTER_ESP: u32 = 0x6824;
537 /// Guest IA32_SYSENTER_EIP.
538 pub const IA32_SYSENTER_EIP: u32 = 0x6826;
539}
540
541/// Fields used to access host-state area.
542pub mod host {
543 // B.1.3.: 16-bit host-state fields
544 /// Host ES selector.
545 pub const ES_SELECTOR: u32 = 0xC00;
546 /// Host CS selector.
547 pub const CS_SELECTOR: u32 = 0xC02;
548 /// Host SS selector.
549 pub const SS_SELECTOR: u32 = 0xC04;
550 /// Host DS selector.
551 pub const DS_SELECTOR: u32 = 0xC06;
552 /// Host FS selector.
553 pub const FS_SELECTOR: u32 = 0xC08;
554 /// Host GS selector.
555 pub const GS_SELECTOR: u32 = 0xC0A;
556 /// Host TR selector.
557 pub const TR_SELECTOR: u32 = 0xC0C;
558
559 // B.2.4.: 64-bit host-state fields
560 /// Host IA32_PAT (full).
561 pub const IA32_PAT_FULL: u32 = 0x2C00;
562 /// Host IA32_PAT (high).
563 pub const IA32_PAT_HIGH: u32 = 0x2C01;
564 /// Host IA32_EFER (full).
565 pub const IA32_EFER_FULL: u32 = 0x2C02;
566 /// Host IA32_EFER (high).
567 pub const IA32_EFER_HIGH: u32 = 0x2C03;
568 /// Host IA32_PERF_GLOBAL_CTRL (full).
569 pub const IA32_PERF_GLOBAL_CTRL_FULL: u32 = 0x2C04;
570 /// Host IA32_PERF_GLOBAL_CTRL (high).
571 pub const IA32_PERF_GLOBAL_CTRL_HIGH: u32 = 0x2C05;
572
573 // B.3.4.: 32-bit host-state field
574 /// Host IA32_SYSENTER_CS.
575 pub const IA32_SYSENTER_CS: u32 = 0x4C00;
576
577 // B.4.4.: natural-width host-state fields
578 /// Host CR0.
579 pub const CR0: u32 = 0x6C00;
580 /// Host CR3.
581 pub const CR3: u32 = 0x6C02;
582 /// Host CR4.
583 pub const CR4: u32 = 0x6C04;
584 /// Host FS base.
585 pub const FS_BASE: u32 = 0x6C06;
586 /// Host GS base.
587 pub const GS_BASE: u32 = 0x6C08;
588 /// Host TR base.
589 pub const TR_BASE: u32 = 0x6C0A;
590 /// Host GDTR base.
591 pub const GDTR_BASE: u32 = 0x6C0C;
592 /// Host IDTR base.
593 pub const IDTR_BASE: u32 = 0x6C0E;
594 /// Host IA32_SYSENTER_ESP.
595 pub const IA32_SYSENTER_ESP: u32 = 0x6C10;
596 /// Host IA32_SYSENTER_EIP.
597 pub const IA32_SYSENTER_EIP: u32 = 0x6C12;
598 /// Host RSP.
599 pub const RSP: u32 = 0x6C14;
600 /// Host RIP.
601 pub const RIP: u32 = 0x6C16;
602}
603
604/// VM-exit information fields.
605pub mod ro {
606 // B.2.2.: 64-bit read-only data fields
607 /// Guest-physical address (full).
608 pub const GUEST_PHYSICAL_ADDR_FULL: u32 = 0x2400;
609 /// Guest-physical address (high).
610 pub const GUEST_PHYSICAL_ADDR_HIGH: u32 = 0x2401;
611
612 // B.3.2.: 32-bit read-only data fields
613 /// VM-instruction error.
614 pub const VM_INSTRUCTION_ERROR: u32 = 0x4400;
615 /// Exit reason.
616 pub const EXIT_REASON: u32 = 0x4402;
617 /// VM-exit interruption information.
618 pub const VMEXIT_INTERRUPTION_INFO: u32 = 0x4404;
619 /// VM-exit interruption error code.
620 pub const VMEXIT_INTERRUPTION_ERR_CODE: u32 = 0x4406;
621 /// IDT-vectoring information field.
622 pub const IDT_VECTORING_INFO: u32 = 0x4408;
623 /// IDT-vectoring error code.
624 pub const IDT_VECTORING_ERR_CODE: u32 = 0x440A;
625 /// VM-exit instruction length.
626 pub const VMEXIT_INSTRUCTION_LEN: u32 = 0x440C;
627 /// VM-exit instruction information.
628 pub const VMEXIT_INSTRUCTION_INFO: u32 = 0x440E;
629
630 // B.4.2.: natural-width read-only data fields
631 /// Exit qualification.
632 pub const EXIT_QUALIFICATION: u32 = 0x6400;
633 /// I/O RCX.
634 pub const IO_RCX: u32 = 0x6402;
635 /// I/O RSI.
636 pub const IO_RSI: u32 = 0x6404;
637 /// I/O RDI.
638 pub const IO_RDI: u32 = 0x6406;
639 /// I/O RIP.
640 pub const IO_RIP: u32 = 0x6408;
641 /// Guest-linear address.
642 pub const GUEST_LINEAR_ADDR: u32 = 0x640A;
643}