Expand description
Information about the xAPIC for the local APIC.
Table 10-1 Local APIC Register Address Map the MMIO base values are found in this file.
Structs§
- XAPIC
- State for the XAPIC driver.
Constants§
- XAPIC_
EOI - EOI register. Write-only.
- XAPIC_
ESR - Error Status Register (ESR). Read/write. See Section 10.5.3.
- XAPIC_
ICR0 - Interrupt Command Register (ICR). Read/write. See Figure 10-28 for reserved bits
- XAPIC_
ICR1 - Interrupt Command Register (ICR). Read/write. See Figure 10-28 for reserved bits
- XAPIC_
ID - Local APIC ID register. Read-only. See Section 10.12.5.1 for initial values.
- XAPIC_
IRR0 - Interrupt Request Register (IRR); bits 31:0. Read-only.
- XAPIC_
IRR1 - IRR bits 63:32. Read-only.
- XAPIC_
IRR2 - IRR bits 95:64. Read-only.
- XAPIC_
IRR3 - IRR bits 127:96. Read-only.
- XAPIC_
IRR4 - IRR bits 159:128. Read-only.
- XAPIC_
IRR5 - IRR bits 191:160. Read-only.
- XAPIC_
IRR6 - IRR bits 223:192. Read-only.
- XAPIC_
IRR7 - IRR bits 255:224. Read-only.
- XAPIC_
ISR0 - In-Service Register (ISR); bits 31:0. Read-only.
- XAPIC_
ISR1 - ISR bits 63:32. Read-only.
- XAPIC_
ISR2 - ISR bits 95:64. Read-only.
- XAPIC_
ISR3 - ISR bits 127:96. Read-only.
- XAPIC_
ISR4 - ISR bits 159:128. Read-only.
- XAPIC_
ISR5 - ISR bits 191:160. Read-only.
- XAPIC_
ISR6 - ISR bits 223:192. Read-only.
- XAPIC_
ISR7 - ISR bits 255:224. Read-only.
- XAPIC_
LDR - Logical Destination Register (LDR). Read/write in xAPIC mode.
- XAPIC_
LVT_ CMCI - LVT CMCI register. Read/write. See Figure 10-8 for reserved bits.
- XAPIC_
LVT_ ERROR - LVT Error register. Read/write. See Figure 10-8 for reserved bits.
- XAPIC_
LVT_ LINT0 - LVT LINT0 register. Read/write. See Figure 10-8 for reserved bits.
- XAPIC_
LVT_ LINT1 - LVT LINT1 register. Read/write. See Figure 10-8 for reserved bits.
- XAPIC_
LVT_ PMI - LVT Performance Monitoring register. Read/write. See Figure 10-8 for reserved bits.
- XAPIC_
LVT_ THERMAL - LVT Thermal Sensor register. Read/write. See Figure 10-8 for reserved bits.
- XAPIC_
LVT_ TIMER - LVT Timer register. Read/write. See Figure 10-8 for reserved bits.
- XAPIC_
PPR - Processor Priority Register (PPR). Read-only.
- XAPIC_
SVR - Spurious Interrupt Vector Register (SVR). Read/write. See Section 10.9 for reserved bits.
- XAPIC_
TIMER_ CURRENT_ COUNT - Current Count register (for Timer). Read-only.
- XAPIC_
TIMER_ DIV_ CONF - Divide Configuration Register (DCR; for Timer). Read/write. See Figure 10-10 for reserved bits.
- XAPIC_
TIMER_ INIT_ COUNT - Initial Count register (for Timer). Read/write.
- XAPIC_
TMR0 - Trigger Mode Register (TMR); bits 31:0. Read-only.
- XAPIC_
TMR1 - TMR bits 63:32. Read-only.
- XAPIC_
TMR2 - TMR bits 95:64. Read-only.
- XAPIC_
TMR3 - TMR bits 127:96. Read-only.
- XAPIC_
TMR4 - TMR bits 159:128. Read-only.
- XAPIC_
TMR5 - TMR bits 191:160. Read-only.
- XAPIC_
TMR6 - TMR bits 223:192. Read-only.
- XAPIC_
TMR7 - TMR bits 255:224. Read-only.
- XAPIC_
TPR - Task Priority Register (TPR). Read/write. Bits 31:8 are reserved.
- XAPIC_
VERSION - Local APIC Version register. Read-only. Same version used in xAPIC mode and x2APIC mode.