Expand description
Description of the data-structures for IA-32e paging mode.
Structs§
- Huge
Page - A type wrapping a huge page with a 1 GiB buffer.
- IOAddr
- A wrapper for an IO address (IOVA / DMA Address for devices)
- Large
Page - A type wrapping a large page with a 2 MiB buffer.
- PAddr
- A wrapper for a physical address.
- PDEntry
- A PD Entry consists of an address and a bunch of flags.
- PDFlags
- PD configuration bits description.
- PDPT
Entry - A PDPT Entry consists of an address and a bunch of flags.
- PDPT
Flags - PDPT configuration bit description.
- PML4
Entry - A PML4 Entry consists of an address and a bunch of flags.
- PML4
Flags - PML4 configuration bit description.
- PML5
Entry - A PML5 Entry consists of an address and a bunch of flags.
- PML5
Flags - PML5 configuration bit description.
- PTEntry
- A PT Entry consists of an address and a bunch of flags.
- PTFlags
- PT Entry bits description.
- Page
- A type wrapping a base page with a 4 KiB buffer.
- VAddr
- A wrapper for a virtual address.
Constants§
- BASE_
PAGE_ SHIFT - Log2 of base page size (12 bits).
- BASE_
PAGE_ SIZE - Size of a base page (4 KiB)
- CACHE_
LINE_ SIZE - Size of a cache-line
- HUGE_
PAGE_ SIZE - Size of a huge page (1 GiB)
- LARGE_
PAGE_ SIZE - Size of a large page (2 MiB)
- MAXPHYADDR
- MAXPHYADDR, which is at most 52; (use CPUID for finding system value).
- MAXVADDR
- Maximum virtual address.
- MAXVADDR_
BITS - Maximum supported bits for virtual addresses (with 5-level paging)
- PAGE_
SIZE_ ENTRIES - Page tables have 512 = 4096 / 64 entries.
- PML4_
SLOT_ SIZE - Size of a region covered by a PML4 Entry (512 GiB)
Functions§
- pd_
index - Given virtual address calculate corresponding entry in PD.
- pdpt_
index - Given virtual address calculate corresponding entry in PDPT.
- pml4_
index - Given virtual address calculate corresponding entry in PML4.
- pml5_
index - Given virtual address calculate corresponding entry in PML5.
- pt_
index - Given virtual address calculate corresponding entry in PT.